1. Field of the Invention
The present invention relates to broadband signal switching networks and is more particularly concerned with such a network with a switching point matrix constructed in field-effect transistor (FET) technology whose inputs are respectively provided with an input driver and whose outputs can be provided with an output driver, whereby the matrix output lines can be charged in each precharge phase via a precharge circuit controlled by a clock signal dividing a bit through connection interval into a precharge phase and an actual through connecting phase, to a precharge potential residing between two operating potentials or also to one of the two operating potentials, and which is particularly characterized in that the output of the respective input driver is connected via a threshold-value holding feedback member with an inhibit input of the input driver by way of the recharging of the output of the respective input driver is terminated.
2. Description of the Prior Art
Modern developments of telecommunications engineering lead to integrated services message transfer and switching systems for narrow band and broadband communication services, which provide light waveguides as transmission media in the region of the subscriber lines by way of which the narrow band communication services, in particular 64 kbit/s digital telephony, as well as broadband communication services, in particular 140 Mbit/s video telephony, are guided, whereby in the switching stations also narrow band signal switching networks and broadband signal switching networks (preferably with joint control units) can be provided adjacent to one another as in the German Letters Patent 24 21 002).
As known from the European published application 0 262 479, a broadband signal switching network has a switching point matrix constructed in FET technology whose switching elements are respectively composed of a switch transistor charged at its control electrode with a through connect signal or a blocking signal and connected with a main electrode to the appertaining matrix output line, whereby the switching elements respectively have one auxiliary transistor in serial connection with the switch transistor which is connected with its control electrode to the appertaining matrix input line and whose main electrode not facing the serial connection is connected via a sampling transistor with the one terminal of the operating voltage source, with whose other terminal the respective matrix output line is connected via a precharge transistor, and whereby a precharge transistor and a sampling transistor are charged oppositely to one another respectively at their control electrodes with a switching network setting clock dividing a bit through connecting phase into a precharge phase and an actual through connecting phase, so that in each precharge phase, given a blocked sampling transistor, the matrix output line is charged via the precharge transistor at least approximately to the potential prevailing at the mentioned other terminal of the operating voltage source. This known broadband signal switching network which can have sampling transistors individually for the switching elements or sampling transistors individually for the matrix input line or matrix output line requires, for the activation/selection of these sampling transistors, their own clock pulse lines throughout the switching joint matrix which requires a corresponding amount of space and is accompanied by a corresponding capacitive load of the matrix output lines. In order to guarantee sufficient protection from interferences, clock distribution and couplings between matrix input lines and matrix output lines require sufficiently-high signal amplitudes on the matrix output lines which is connected with a relatively high power consumption.
As suggested in the European application 88 11 2908.4, a broadband signal switching network with a switching point matrix constructed in FET technology whose inputs can be provided with an input driver and whose outputs are provided with an output amplifier, whose switching elements, respectively controlled by a hold memory cell, are composed of a serial connection of a switch transistor charged at its control electrode with a through connect or blocking signal and an input transistor connected with its control electrode to the appertaining matrix input line, which is connected with the main electrode not facing the serial connection of the one transistor to the appertaining matrix output line. The matrix output line is connected with a precharge potential source via a precharge circuit which is connected with an unblocking input to the clock signal line of a precharge clock signal defining the precharge phase of a bit through connecting interval divided into a precharge phase and the rest of the bit through connecting interval, so that the matrix output line is charged to a precharge potential in each precharge phase. This arrangement provides a swing limitation of the signal on the output lines of the switching network. For that, the main electrode, not facing the serial connection, of the other transistor of each switching element is connected with the one terminal of the operating voltage source via a transistor provided individually for the matrix output line and connected at its control electrode with the output of an output amplifier circuit provided individually for the matrix output line. Given a change of the signal state at the output of the output amplifier, this transistor is blocked and therefore a further recharging of the output line is prevented, whereby the signal swing on the output line is limited.
A noticeable disadvantage of the known broadband signal switching networks is that a large portion of the required energy must be used for the recharging of the input lines of the switching point matrix.